The present invention relates to an integrated circuit substrate and, more particularly, to a ball grid array package that accommodates a lead-on-chip architecture.
An integrated circuit lead frame generally consists of a die paddle for mounting the integrated circuit (IC), leads that connect the integrated circuit to the package exterior, and a support structure that holds the frame together through the assembly operation. There are various configurations of lead frames currently in use in the semiconductor packaging industry including lead-on-chip (LOC) and lead-under-chip (LUC) configurations. These LOC packages have a unique mechanical configuration that, when assembled, best accommodate the needs of memory architecture.
Memory architecture is heavily influenced by the objective of providing an evenly distributed I/O channel (bus) across all the memory cells within the device. Desired characteristics driving this include lower operating voltages, which make the device more sensitive to voltage drops (spikes), higher gate densities, faster access times, and increased clock speeds (shorter paths). Thus, a large number of memory devices are typically designed with the I/O interface (aluminum bond pads) in a row bisecting the active side of the die. This centerline configuration provides minimized power, ground, and signal paths to every cell within the structure. LOC designed packages uniquely accommodate the I/O interface with a centerline bond configuration fanning out to perimeter leads.
A basic LOC package structure employs an etched or stamped lead frame that incorporates a centerline slot into a die paddle. The die paddle is connected to the leads and the frame via a tie bar that is eventually removed. During package assembly, the die is mounted against the die paddle with the active side (I/O side) down against the paddle base, leads on the opposite side. Package assemblers use a variety of die attachment methods, including tape and liquid adhesive. As the die is mounted, the I/O connections (aluminum bond pads) on the die are left exposed on the opposite side via the centerline slot. The bond pads are then electrically connected to the leads via conventional Au wire bond techniques. Once the device is wired, the structure can be overmolded or liquid encapsulated to protect the silicon and wires. The superstructure (frame and tie bars) can then be removed, if not removed already, and the devices are left singulated from the frame. The end configuration of the device can take numerous shapes based on lead frame technology used, but varieties include a small outline package (SOP), small outline integrated circuit (SOIC), plastic leaded chip carrier (PLCC) or a thin shrink small outline package (TSSOP). The lead frame technology and assembly techniques described are widely used within the industry.
Over the past five years, silicon trends have placed greater demands on the electrical, thermal, and reliability performance these LOC devices. One such trend relates to the gate densities now being achieved in the silicon itself. As device geometries decrease, the gate densities of memory devices have increased dramatically. Increased gate density translates into higher power concentration in smaller areas, which means more heat. Most LOC packages manage this heat by using a metal die pad, but the heat dissipation performance is reduced by the plastic encapsulant, a poor heat conductor, and the small surface area of the leads through which the heat is transmitted. Failure to properly manage the heat generated by the integrated circuit can result in an accelerated failure of the device circuitry.
A second trend stressing conventional LOC packaging is clock speed. The system""s need for faster access times and greater bandwidth have driven memory clock speeds into the microprocessor realm of near and over 1 gigahertz. These clock speeds demand improved (lower) line inductance, power/ground networks, and shielding that plastic LOC packages cannot deliver due either to materials sets and/or lead configuration limitations. Finally, high-speed memory is permeating many high performance systems where the reliability of plastic (moisture absorbing) LOC packages comes into question.
Additionally, recent manufacturing trends have further compromised the effectiveness of traditional LOC packages. These trends involve the transition from traditional leaded integrated circuit packages to ball grid array (BGA) integrated circuit packages in a majority of high performance silicon applications. The main drivers of this trend include improved surface mountability, smaller package footprints, greater package densities, and growing assembly infrastructures. A need has thus arisen for a new LOC substrate solution for high speed memory packaging that has the advantages of a BGA package and has enhanced thermal and electrical properties. These and other needs are satisfied by the ball grid array substrate package of the present invention.
A package substrate suitable for use with a ball grid array according to the invention includes an electrically and thermally conductive heat sink having a top surface and a bottom surface, the heat sink having a slot formed therethrough which opens onto the top and bottom surfaces. A dielectric layer is formed on the bottom surface of the heat sink proximate the slot, preferably directly thereon without an intervening adhesive layer. A circuit is selectively formed in a circuit pattern on the dielectric layer. An electrically resistive soldermask is disposed on the dielectric layer and the circuit, which soldermask has openings therethrough which expose bond pads of the circuit. Such a substrate according to the invention permits the integrated circuit die to be mounted over the slot in the manner of a lead-on-chip package, but provides bond pads to which solder balls can be mounted in order to form a ball grid array. A layer of an adhesive, such as in a tape form, may be cut to size and secured to the top surface of the heat sink proximate the slot, eliminating the need for the user to apply the adhesive during the process of mounting the die.
According to preferred embodiments of the invention, the substrate includes one or more vias filled with electrically and thermally conductive material, which vias extend through the dielectric layer and accessible through the soldermask layer, and are typically located outside of the circuit pattern. Solder balls may be connected to these filled vias in order to permit grounding of the heat sink to the motherboard and permit heat from the integrated circuit die to pass through the heat sink and via to the motherboard. In addition, a portion of the bottom surface of the heat sink adjacent the slot may be left exposed, such as by selective removal of the dielectric coating, for connection to a ground wire connected to the die. Such a ground wire can pass heat directly from the die to the heat sink, after which it can pass through the filled via into the motherboard.
A new lead frame, or xe2x80x9cball framexe2x80x9d according to the invention captures the assembly advantages of LOC type packages and addresses the shortcomings described above. The lead frame is improved by incorporation of a dielectric and circuit layer on the side opposite the die. This configuration can provide thermal management, active power and ground networks, and a ball grid array pin-out, while accommodating existing and foreseeable die sizes. Such a lead frame of the invention preferably comprises a strip of package substrates as described above formed side by side and connected on the ends by rails. Each package substrate may be separated from each adjacent package substrate by an elongated widthwise slot having a greater length than the slot in the heat sink. The strip is cut both vertically and horizontally at the time of use to yield separate package substrates.
The invention further provides a method for manufacturing a substrate package. According to this method, the bottom surface of the heat sink is first treated with an adhesion promoter, and the dielectric layer is then formed directly on the treated bottom surface. A circuit pattern is then formed on the dielectric layer, preferably by electrolytic deposition. An electrically resistive soldermask is then formed over the dielectric layer and circuit, and portions of the soldermask are then selectively removed to expose wire bonding pads and ball pads on the circuit. Optionally, a via may be formed through the dielectric layer and filled with an electrically and thermally conductive material, and a further portion of the soldermask is selectively removed to expose and permit access to the filled via. A slot is formed in the heat sink at a location adjacent the wire bonding pads, which slot opens onto top and bottom surfaces of the heat sink. Optionally, the adhesive layer for attaching the die may be pre-applied by cutting an adhesive sheet into a preform which has an opening therein of the same shape as the slot, and applying the preform to the top surface of the heat sink so that the preform opening is in alignment with the slot. The substrate may then be shipped to an end user for completion. If a ground wire is to be run from the die directly to the heat sink as described above, then the process further includes a step of exposing an edge of the bottom surface of the heat sink adjacent the slot. The foregoing steps are preferably performed on a series of substrates in strip form in order to produce a lead frame according to the invention.
The end user completes the integrated circuit package using a package substrate made by the foregoing process. If not already present, an adhesive is applied to the top surface of the heat sink around the slot, and an integrated circuit die is mounted to the top surface of the heat sink by means of the adhesive, such that wire bond pads on the die are exposed in the slot. Electrically conductive wires are bonded to the wire bond pads on the die and to the wire bond pads of the circuit adjacent the slot. The wires and die are then covered with an encapsulant, and solder balls are bonded (soldered) to the ball pads. The integrated circuit packages by then be singulated by cutting the lead frame as mentioned above. These and other aspects of the invention are described further in the detailed description that follows.